This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-186995, filed Jun. 30, 1999; and No. 2000-175512, filed Jun. 12, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device in which a well under the channel of a MISFET is electrically connected to a gate electrode, and a method of manufacturing the same.
Conventionally, to reduce power consumption of a semiconductor device, a power supply voltage Vdd is continuously dropped. However, a threshold voltage Vth of a MISFET is not so largely dropped in order to prevent any increase in OFF-current. Hence, a driving capability (drain current) Id of a transistor tends to be low.
As a device for solving this problem, a DTMISFET (Dynamic Threshold Voltage Metal insulator Semiconductor Field Effect Transistor) has been proposed (Fariborz Assaderaghi, et al, xe2x80x9cDynamic threshold-voltage MOSFET (DTMOS) for Ultra-Low voltage VLSIxe2x80x9d, IEEE Trans. Electron Devices, Vol. 44, pp. 414-421, 1997).
The structure of a DTMISFET (DTMOSFET) will be described with reference to FIGS. 26A and 26B. FIG. 26A is a perspective view showing the structure of a conventional DTMISFET. FIG. 26B is a cross-sectional view showing a section taken along a line V-Vxe2x80x2 in FIG. 26A. Referring to FIGS. 26A and 26B, reference numeral 3500 denotes an SOI substrate; 3501, an Si substrate; 3502, an insulating layer; 3503, an Si-body (well region); 3504, an n+-type source and drain; 3505, a gate insulating film; 3506, a gate electrode made of polysilicon; and 3507, a p+type diffusion layer serving as a contact to a metal plug 3508 connected to the gate electrode.
A DTMISFET is a MISFET in which the gate electrode and the well (Si-body) under the channel are electrically connected and has an advantage that although a power supply voltage Vdd is low, the driving capability is large, and the OFF current is small. The reason for this advantage is explained by the principle of operation in which the gate voltage is transmitted to the substrate to generate the substrate bias effect, so a threshold voltage Vth is low in the transistor ON state and high in the OFF state.
The device also has the following advantages.
(1) One of reasons why the DTMISFET can realize a high driving capability is that the vertical electric field perpendicular to the channel plane is small, and carrier mobility is large.
(2) The S-factor always has an ideal value of approximately 60 mV/decade (best value at room temperature) in a region where no short channel effect occurs.
(3) A low threshold voltage Vth that is suggested to be unrealizable by a MISFET using a metal gate electrode (e.g., gate using TiN) with a midgap work function can be realized.
However, a DTMISFET has the following disadvantages and therefore is not put into practical use for a long time.
(1) To form the contact area (contact hole and metal plug) connecting between polysilicon gate electrode and the Si-body, the device occupation area increases to result in complex manufacturing process. As shown in FIG. 27, when two contacts for connecting the gate and well region are formed for one transistor, the device occupation area increases. Contact holes are formed on both the left and right sides of the Si-body 3502 to reduce the resistance in the Si-body portion. The same reference numerals as in FIGS. 26A and 26B denote the same parts in FIG. 27, and a detailed description thereof will be omitted.
(2) The high body resistance causes RC delay in the gate wiring, which readily adversely affects the circuit operation.
(3) The source/drain junction capacitance is larger than that of a conventional MOSFET.
(4) A forward bias applied to the p-n junction between the source/drain and the Si-body, and when the power supply voltage Vdd exceeds about 0.7 V, the leakage current increases to make the device unusable.
In recent years, to reduce the p-n junction leakage between a source/drain and an Si-body, an attempt of connecting a gate and body via a capacitor has been proposed (IEEE International Solid-State Circuits Conference Digest of Technical Papers, p. 292, 1997). However, an increase in device area due to capacitor formation poses a serious problem (as described in the above reference, a p-n junction diode also need to be formed when we connect a gate and body via a capacitor).
It is an object of the present invention to provide a semiconductor device capable of reducing the occupation area of a DTMISFET and simplifying the manufacturing process, and a method of manufacturing the same.
In order to achieve the above object, the present invention has the following arrangements.
According to the present invention, there is provided a semiconductor device formed on a semiconductor substrate in which a gate electrode of a MISFET is electrically connected to a well region under a channel of the MISFET, wherein the MISFET is formed in an island-shaped element region formed on the semiconductor substrate, and electrical connection between the gate electrode of the MISFET and the well region are electrically connected via a sides of the island-shaped element.
According to the present invention, there is provided a semiconductor device in which a semiconductor substrate including an island-shaped element region comprised of a lower structure and an upper structure formed on the lower structure and having a smaller cross-sectional area parallel to a surface of the substrate than that of the lower structure; a gate insulating film formed on an upper surface of the upper structure of the element region; a sidewall insulating film formed on an upper surface of the lower structure and along a side surface of the upper structure of the element region; and a gate electrode connected to an upper surface of the gate insulating film, an upper surface of the sidewall insulating film, and a side surface of the lower structure of the element region.
According to the present invention, there is provided a semiconductor device in which a semiconductor substrate including an island-shaped element region composed of a lower structure and an upper structure formed on the lower structure and having a smaller cross-sectional area parallel to a surface of the substrate than that of the lower structure; a gate insulating film formed on an upper surface of the upper structure of the element region; a gate electrode formed on the gate insulating film; an element sidewall insulating film formed along a side of the upper structure of the element region and a side of the gate electrode that have an upper surface lower than an upper surface of the gate electrode; and a contact electrode formed on a side of the lower structure of the element region and a side of the sidewall insulating film and electrically connected to the gate electrode and the side of lower structure of the element region.
According to the present invention, there is provided a semiconductor device in which a semiconductor substrate including an island-shaped element region comprised of a lower structure and an upper structure formed on the lower structure and having a smaller cross-sectional area parallel to a surface of the substrate than that of the lower structure; a gate insulating film formed on an upper surface of the upper structure of the element region; a sidewall insulating film formed on a side of the upper structure of the element region; a capacitor insulating film formed on each of opposite sides of the lower structure of the element region; a gate electrode formed on the gate insulating film; and a capacitor electrode formed on the capacitor insulating film and electrically connected to the gate electrode.
According to the present invention, there is provided a semiconductor device formed on a semiconductor substrate in which a gate electrode of a MISFET is electrically connected to a well region under a channel of the MISFET, wherein the MISFET is formed on part of a side of an island-shaped element region formed on the semiconductor substrate, and electrical connection between the gate electrode of the MISFET and the well region in the semiconductor substrate is done on an upper surface of the island-shaped element region.
According to the present invention, there is provided a semiconductor device in which a semiconductor substrate including an island-shaped element region composed of a lower structure and an upper structure formed on the lower structure and having a smaller cross-sectional area parallel to a surface of the substrate than that of the lower structure; a pair of gate insulating films formed on opposite sides of the lower structure of the element region, respectively; a sidewall insulating film formed on a side surface of the upper structure of the element region; a gate electrode formed on the pair of gate insulating films, an upper surface of the sidewall insulating film, and an upper surface of the upper structure of the element region; and source and drain regions formed on opposite side surfaces of the lower structure of the element region across the pair of gate insulating films, wherein bottom surfaces of the source and drain diffusion layers formed on side surfaces of the element region are in contact with each other.
In the above six semiconductor devices, the gate electrode is preferably composed of a metal material.
According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of patterning a semiconductor substrate to form an island-shaped element region comprised of a lower structure and an upper structure formed on the lower structure and having a smaller cross-sectional area parallel to a surface of the substrate than that of the lower structure, forming an insulating film along a side of the upper structure and an upper surface of the lower structure of the element region, forming a disposable gate in a region on upper where a gate electrode is to be formed, forming a source and drain in the upper structure of the element region, forming an interlayer insulating film on the semiconductor substrate to expose an upper surface of the disposable gate close both sides of the disposable gate, removing the disposable gate to form a gate groove, forming a gate insulating film on an upper surface of the upper structure of the element region, the upper surface being exposed to a bottom surface of the gate groove, and forming a gate electrode buried in the gate groove and electrically connected to a side surface of the lower structure of the element region.
According to the present invention, there is also provided a method of manufacturing a semiconductor device, comprising the steps of forming a mask pattern in a region, where a source, drain, and channel of a MIS transistor are to be formed, on an upper surface of a semiconductor layer formed on stacked a semiconductor substrate and an insulating layer, etching the semiconductor layer using the mask pattern as a mask to form a convex on the semiconductor layer, forming a first sidewall insulating film on a side surface of the convex of the semiconductor layer, etching the semiconductor layer using the mask pattern and the first sidewall insulating film as a mask to expose the insulating layer, thereby forming an island-shaped element region comprised of an upper structure formed from the convex and a lower structure formed under the upper structure, forming a second sidewall insulating film on a side surface of the lower structure of the element region and a side surface of the first sidewall insulating film, forming a disposable gate, on upper surfaces of the insulating layer where the gate electrode is to be formed, the second sidewall insulating film, the first sidewall insulating film, and the upper structure of the element region, forming the source and drain in the upper surface of the upper structure of the element region, forming an insulating film to cover the disposable gate and planarizing an upper surface of the insulating film to expose the disposable gate, removing the disposable gate to form a gate groove in which the side surface of the lower structure of the element region is exposed, forming a gate insulating film on an upper surface of the upper structure of the element region on a bottom surface of the gate groove, and forming a gate electrode buried in the gate groove.
According to the present invention, there is also provided a method of manufacturing a semiconductor device, comprising the steps of forming a mask pattern in a region on a semiconductor layer on a semiconductor substrate, where a source, drain, and channel of a MIS transistor will be formed, etching the semiconductor layer using the mask pattern as a mask to form a convex on the semiconductor layer, forming a first sidewall insulating film on a side of the convex of the semiconductor layer, etching the semiconductor layer using the mask pattern and the first sidewall insulating film as a mask to expose the insulating layer, thereby forming an island-shaped element comprised of an upper structure formed from the convex and a lower structure formed under the upper structure, forming an insulating layer to cover an upper surface of the semiconductor substrate outside the element region so as to expose an upper end portion of a side surface of the lower structure of the element region, forming a second sidewall insulating film on a side surface of the lower structure of the element region and a side surface of the first sidewall insulating film, forming a disposable gate, on upper surfaces of the insulating layer where the gate electrode is to be formed, the second sidewall insulating film, the first sidewall insulating film, and the upper structure of the element region, forming the source and drain in the upper surface of the upper structure of the element region, forming an insulating film to cover the disposable gate and planarizing an upper surface of the insulating film to expose the disposable gate, removing the disposable gate to form a gate groove connected to the side surface of the lower structure of the element region, forming a gate insulating film on an upper surface of the upper structure of the element region on a bottom surface of the gate groove, and forming a gate electrode buried in the gate groove.
According to the present invention, there is also provided a method of manufacturing a semiconductor device, comprising the steps of forming a mask pattern in a region, where a source, drain, and channel region of a MIS transistor are to be formed, on an upper surface of a semiconductor layer formed on stacked a semiconductor substrate and an insulating layer, etching the semiconductor layer to a predetermined depth using the mask pattern as an etching mask to form a convex on the semiconductor layer, forming an element sidewall insulating film on side surfaces of the mask pattern and the convex of the semiconductor layer, etching the semiconductor layer using the mask pattern and the element sidewall insulating film as a mask to expose the insulating layer, thereby forming an island-shaped element region comprised of an upper structure formed from the convex and a lower structure formed under the upper structure, forming a dummy contact on a side surface of the lower structure of the element region and a side surface of the element sidewall insulating film, forming a first insulating film around the dummy contact, recessing an upper surface of the element sidewall insulating film, partially or completely removing the mask pattern, forming a disposable gate connected to the dummy contact on an upper surface of a region where a gate electrode is to be formed, including the channel region of the upper structure of the element region, forming the source and drain in the upper structure of the element region using the disposable gate as a mask, forming a second insulating film on the semiconductor substrate to cover a side surface of the disposable gate and expose an upper surface of the disposable gate, removing the disposable gate to form a gate groove in which the dummy contact is exposed, forming a gate insulating film in the gate groove, forming a gate electrode buried in the gate groove, exposing the upper surface of the dummy contact, removing the dummy contact to form a contact trench in which the side surface of the lower structure of the element region is exposed, and forming a contact electrode buried in the contact trench.
According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a mask pattern in a region, where a source, drain, and channel region of a MIS transistor are to be formed, on a semiconductor substrate, etching the semiconductor substrate to a predetermined depth using the mask pattern as an etching mask to form a convex on the semiconductor substrate, forming an element sidewall insulating film on side surfaces of the mask pattern and the convex, etching the semiconductor layer using the mask pattern and the element sidewall insulating film as a mask to form an island-shaped element region comprised of an upper structure formed from the convex and a lower structure formed under the upper structure, forming a dummy contact on a side surface of the lower structure of the element region and a side surface of the element sidewall insulating film, forming a first insulating film around the dummy contact, recessing an upper surface of the element sidewall insulating film, partially or completely removing the mask pattern, forming a disposable gate connected to the dummy contact on an upper surface of a region where a gate electrode is to be formed, including the channel region of the upper structure of the element region, forming the source and drain in the upper structure of the element region using the disposable gate as a mask, forming a second insulating film on the semiconductor substrate to cover a side surface of the disposable gate and expose an upper surface of the disposable gate, removing the disposable gate to form a gate groove in which the dummy contact is exposed, forming a gate insulating film in the gate groove, forming a gate electrode buried in the gate groove, exposing the upper surface of the dummy contact, removing the dummy contact to form a contact trench in which part of a sidewall is connected to the side surface of the lower structure of the element region, and forming a contact electrode buried in the contact trench.
According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising forming a mask pattern in a region on a semiconductor substrate, where a source, drain, and channel region of a MIS transistor are to be formed; etching the semiconductor substrate to a predetermined depth using the mask pattern as a mask to form a convex on the semiconductor substrate; forming a sidewall insulating film on side surfaces of the mask pattern and the convex; etching the semiconductor layer using the mask pattern and the element sidewall insulating film as a mask to form an island-shaped element region comprised of an upper structure formed from the convex and a lower structure formed under the upper structure; forming a disposable gate in a region on the semiconductor substrate, where a gate electrode is to be formed; forming the source and drain in the upper structure of the element region; forming an interlayer insulating film on the semiconductor substrate in contact with the disposable gate to expose an upper surface of the disposable gate; removing the disposable gate to form a gate groove in which the element region is partially exposed; depositing an insulating film on an upper surface of the element region exposed to a bottom surface of the gate groove so as to form a gate insulating film on the upper structure of the element region and form a capacitor insulating film on a side surface of the lower structure of the element region; and burying an electrode pattern in the gate groove to form a gate electrode and capacitor electrode.
According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising forming a mask pattern in a region on a semiconductor substrate, where a source, drain, and channel region of a MIS transistor are to be formed; etching the semiconductor substrate to a predetermined depth using the mask pattern as a mask to form a convex on the semiconductor substrate; forming a sidewall insulating film on side surfaces of the mask pattern and the convex; etching the semiconductor layer using the mask pattern and the element sidewall insulating film as a mask to form an island-shaped element region comprised of an upper structure formed from the convex and a lower structure formed under the upper structure; forming a disposable gate in a region on the semiconductor substrate, where a gate electrode is to be formed; forming the source and drain in a side portion of the lower structure of the element region; forming an interlayer insulating film on the semiconductor substrate in contact with a side portion of the disposable gate to expose an upper surface of the disposable gate; removing the disposable gate to form a gate groove in which the element region is partially exposed; forming a gate insulating film on a side surface of the lower structure of the element region exposed to a bottom surface of the gate groove; and forming a gate electrode buried in the gate groove.
The present invention with the above arrangements has the following functions and effects.
Since the gate electrode and well region are electrically connected on the side surface of the island-shaped element region, the planar area of a contact formation portion is unnecessary, unlike the conventional DTMISFET, so the device occupation area can be largely reduced. In addition, since the portion for electrically connecting the gate electrode and well region is formed by self-alignment, the manufacturing process can be simplified.
In addition, when the gate and Si-body are electrically connected via a capacitor formed on the side surface of an island-shaped element region Si, the area can be reduced, and the leakage current between the source/drain and the Si-body can be largely decreased.
Furthermore, since the source and drain diffusion layers are formed to sandwich two gate electrodes formed at the side portion of the island-shaped element region, and the bottom portions of the source and drain diffusion layers come into contact with each other, the p-n junction area can be reduced, and the leakage current between the source/drain and the Si-body can be largely decreased.
When a metal electrode is used as a gate electrode, electrical connection to both an n-type well and a p-type well is facilitated. In use of a polysilicon gate electrode, when a gate is to be connected to a well region of conductivity type opposite to that of the gate, a metal plug must be formed therebetween. However, when a metal gate electrode is used, no metal plug need be formed.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.